In microminature electronic circuitry, it is desirable that a large number of integrated circuit chips be packaged and interconnected so that they can perform functions in the minimum of time. Up until the present time integrated circuits have been virtually exclusively packaged on substrates with the integrated circuit chips parallel to the substrate. This type of structure has always seemed to be the only way of joining a semiconductor chip to a module when it is understood by those skilled in the art that the integrated circuit semiconductor chip size is of the order of hundreds of square mils on a side.
There has been attempts to increase the density of integrated circuit chips in a package by attaching a plurality of semiconductor chip carrying substrates vertically onto a main substrate. In this structure the semiconductor chips are vertically held and the density of the package in terms of integrated circuit chips has increased. Examples of these designs can be seen in the M. Bennett, et al U.S. Pat. No. 3,916,266, W. Anacker, U.S. Pat. No. 3,949,274, B. Agusta, et al IBM Technical Disclosure Bulletin Vol 10, No. 7, December 1967, pp. 890 and 891 and B. R. Kryaniwsky, IBM Technical Disclosure Bulletin Vol 14, No. 10, March 1972, page 2911.
The M. Bennett, et al patent describes a package for interconnecting a plurality of integrated circuit chips which includes a dielectric body having a plurality of intersecting planes and a plurality of metalized interconnection patterns located on the planes. The integrated circuit chips are mounted onto the metalized interconnecting patterns. These interconnecting patterns extend to a base member wherein terminals are provided for interconnection off of the package.
The Anacker patent describes a package for interconnecting superconductive circuitry of the Josephson type. Superconductive circuit chips are attached by solder reflow techniques to conductors formed upon a substrate which may be composed of silicon or glass or other suitable material, and this substrate is mounted on along with other superconducting circuit chip carrying substrates on a principal substrate.
The Agusta, et al IBM Technical Disclosure Bulletin describes a similar structure to that of Anacker for integrated circuits wherein the principal module substrate carries a plurality of chip carriers which have integrated circuit chips mounted thereon. This concept shows the interconnection of chip carriers by means other than the principal module substrate.
The Kryaniwsky IBM Technical Disclosure Bulletin shows a structure where semiconductor chips are mounted in a back-to-back relationship with an intervening air gap which acts as an air column for cooling purposes. The semiconductor chips are epoxy bonded to a chip support member for mechanical strength. The semiconductor chips are electrically connected to the principal substrate by means of conductive line of a printed circuit decal which is folded into a "U" shape so as to be able to contact the back-to-back chips.